The present invention relates to a serial-to-parallel converter (SPC) for converting a serial signal with a predetermined bit rate into a parallel signal with a predetermined bit width.
A conventional SPC includes a shift register and a latch circuit. A shift register is made up of a plurality of flip-flops (FF) connected in series to each other. A serial signal with a predetermined bit rate is input to an initial-stage FF. In response to a common shift clock signal at a frequency matched with the bit rate of the serial signal, each FF operates to forward its input signal to an FF on the next stage. On the other hand, responsive to a latch clock signal at a frequency lower than that of the shift clock signal, the latch circuit latches the respective output signals of the FFs at a time, thereby outputting a parallel signal based on the results of latching.
In the conventional SPC, if the bit rate of the serial signal is very high, however, the shift register might operate erroneously. For example, if the bit rate of the serial signal is 1 Gbps, then each FF included in the shift register should operate at a very high speed in response to a shift clock signal with a frequency as high as 1 GHz. Accordingly, it is difficult to prevent the shift register from operating erroneously.